Browse Prior Art Database

Forming Dielectric Isolation

IP.com Disclosure Number: IPCOM000089068D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Poponiak, MR: AUTHOR [+2]

Abstract

Standard semiconductor processing is utilized to form a device wafer containing subisolation, subcollector and an epitaxial layer. A thin 300-500 angstroms Si(3)N(4) layer 10 is then deposited on the bare epitaxial layer surface 12 preferably at a temperature greater than 800 degrees C. A layer 14 of pyrolytic SiO(2) is deposited over the layer 10. The recessed oxide insulation (ROI) regions are opened through the silicon nitride layer 10 and a silicon trench etched, if desired. The isolation silicon dioxide layer 16 of 5000 to 10000 angstroms is grown to produce Fig. 2. Micrographs of the Fig. 2 structure show virtually no bird's beak. Infrared microscopy along with transmission electron microscopy analysis show no defect generation under the Si(3)N(4).

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Forming Dielectric Isolation

Standard semiconductor processing is utilized to form a device wafer containing subisolation, subcollector and an epitaxial layer. A thin 300-500 angstroms Si(3)N(4) layer 10 is then deposited on the bare epitaxial layer surface 12 preferably at a temperature greater than 800 degrees C. A layer 14 of pyrolytic SiO(2) is deposited over the layer 10. The recessed oxide insulation (ROI) regions are opened through the silicon nitride layer 10 and a silicon trench etched, if desired. The isolation silicon dioxide layer 16 of 5000 to 10000 angstroms is grown to produce Fig. 2. Micrographs of the Fig. 2 structure show virtually no bird's beak. Infrared microscopy along with transmission electron microscopy analysis show no defect generation under the Si(3)N(4). The Si(3)N(4) can now be removed in a H(3)PO(4) -H(2)SO(4) solution (90-10%) at 165-180 degrees C. This etch has the unique property of not deteriorating the silicon surface. After the Si(3)N(4) is removed, an epitaxial re-oxidation is grown to produce silicon dioxide layer 18 (Fig. 3). The wafers are now fabricated according to standard procedures.

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