Browse Prior Art Database

Disturbance Reduction Techniques

IP.com Disclosure Number: IPCOM000089074D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Waucukauski, JA: AUTHOR

Abstract

Reference is made to U. S. Patent 3,761,695 and particularly to Fig. 8 thereof, shown above.

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Disturbance Reduction Techniques

Reference is made to U. S. Patent 3,761,695 and particularly to Fig. 8 thereof, shown above.

A technique for reduction of tester-induced disturbs for Level Sensitive Scan Design (LSSD) part numbers is disclosed. These disturbs are primarily caused by simultaneous high switching activity at the primary outputs, which results in latches receiving incorrect values due to noise coupling or power supply compression. Failures will then occur if measurements are made which depend on these latch values. Therefore, to eliminate failures due to disturbs, it is necessary to eliminate patterns with high switching activity which occur at times when latch values are critical for measurements.

High switching activity most likely occurs at either the

Primary Input, Primary Output (PI,PO) pattern or the turn-off inhibit pattern. Each requires a different solution.
I. Elimination of disturbs at the PI,PO pattern:

Solution: Nonsteady state PI changes normally occurring at the PI,PO pattern are placed just prior to scan-in. Disturbs, if any, will now occur before scan-in and all latches will be refilled before any measurements are made.
II. Elimination of disturbs at the turn-off inhibit pattern when inhibit

status changes.

Solution: One of the following will be selected:
A. Scan-out with inhibit on. This method is used

when scan-out PO is not inhibited.
B. Transition pattern. Prior to turn-off inhibit pattern, an

additional pattern is added which places nonstable state

PI's at values such that a maximum number of PO's remain

at the inhibited state when inhibit is...