Browse Prior Art Database

Test Site for a Semiconductor Masterslice

IP.com Disclosure Number: IPCOM000089075D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Esposito, RM: AUTHOR [+6]

Abstract

A word/bit line structure is used to form the test site for semiconductor masterslice wafers.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 74% of the total text.

Page 1 of 2

Test Site for a Semiconductor Masterslice

A word/bit line structure is used to form the test site for semiconductor masterslice wafers.

Each masterslice chip contains a number of different types of transistors which include logic, receiver and driver functions. The test site is ordinarily fabricated on one or more separate chips on the wafer.

The figure is a schematic of the transistors and test pads in the test sites. As illustrated, the test site layout comprises groups of transistor pairs of the same type in each vertical column and of different types in each row. In the horizontal direction, the respective emitters (EM) and those portions of the subcollectors (SC) which lie under the resistor beds of all transistors in each row (EF3, CS3...) are connected in common to associated pads. In the vertical direction, the collectors of the same type of transistors are connected in common. The bases of all transistors in each half of the chip are also connected in common to pads 1 and 19, respectively. Alternatively, the bases could be connected by quadrant or in toto.

This layout allows the identification of pipes to be localized to one out of two transistors. For example, pipes in one of the two transistors in row 1, column EF3 may be detected through pads 9 and 14. The locations of random and clustered defects may also be identified. By our technique of wiring the subcollectors in common, the integrity of the recessed isolation wall between the resistors and trans...