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Clock Drier and Dual Phase Receiver

IP.com Disclosure Number: IPCOM000089078D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Montegari, F: AUTHOR

Abstract

This is a clock driver and dual-phase receiver implemented in transistor-transistor logic (T/2/L).

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Clock Drier and Dual Phase Receiver

This is a clock driver and dual-phase receiver implemented in transistor- transistor logic (T/2/L).

Referring to the drawing, when input node A is at a down level, current flows through resistor R3 into the base of multiemitter transistor T1, and turns T1 on. The indicated negative voltages have absolute values as follows: V1 < V2 < V3 < V4 so that V4 is the most negative. Since the emitters of transistor T2 and transistor T3 are at a higher (more positive) voltage than emitter A of Tl, the base bias is insufficient to turn them on so that T2 and T3 are off. Since T3 is off, the base of transistor T4 is brought to an up level, causing transistor T4 to turn on. When node A is brought to an up level, T1 is turned off and the current through resistor R3 will flow into the base of T3, turning T3 on, which then turns T4 off. T1 turning off causes T2 to turn on. The resistance values are arranged such that R1 = R4 = R5 while R2 = R3. R2 and R3 each have an impedance that is twice that of R1, R4 and R5. The unequal value of resistors R2 and R4 improves the symmetry of the output waveforms.

The rising transition of either phase always leads the falling transition of the opposite phase at all input rise times. This guarantees hazard-free operation with any type latch and eliminates the need for a direct coupled inverter to prevent race conditions.

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