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Browse Prior Art Database

Latched Inverter Buffer Circuit

IP.com Disclosure Number: IPCOM000089079D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 80K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+2]

Abstract

This is a low power, high speed circuit providing buffered and inverted pulses from short time duration input pulses.

This text was extracted from a PDF file.
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Latched Inverter Buffer Circuit

This is a low power, high speed circuit providing buffered and inverted pulses from short time duration input pulses.

The circuit illustrated in Fig. 1 is capable of receiving relatively low input logic levels of the type customary with bipolar transistor circuits, and provides true and complement output logic levels of a greater voltage swing customary for FET circuits. All voltage levels in the circuit are latched as the circuit is selected.

Power dissipation is low due to the voltage on the linear stages being reduced during standby, and the linear stage that is not required, when the chip is selected, is disabled. High noise immunity is provided due to all nodes being latched, the linear stage not required being discharged during the occurrence of the select input signal. This circuit is uniquely adapted to be a storage address register (SAR), providing buffered and inverted pulses to be used for decoding from an input address that is valid for only a short time interval.

Fig. 1 illustrates the circuit diagram, while Fig. 2 is a set of waveform diagrams depicting the operation of the circuit. During standby, the input terminals PC, BOOST, R1 and R2 are at up levels so that transistors T1, T2, T3, T4, T11, T12, T17, T18 and T21 are all conditioned to be on. The SELECT input terminal is at a down level so that transistor T23 is conditioned off. Series- connected devices T1 and T4, as well as series-connected devices T2 and T3 are designed with width-to-length (W/L) ratios to provide an intermediate voltage level at nodes A and B, when the BOOST input is at +V and the PC input is at +V-Vt. (Vt refers to the threshhold voltage level.)

The up-level input at terminals R1 and R2 holds nodes C and D as well as the two output nodes to ground potential by means of devices T11, T12, T17 and T18 which are on. With node R1 at an up level and the select input terminal at a down level, node NI is at +V-Vt. At this point in time, series-connected devices T1, T4 and T2, T3 conduct current, but these all have a high impedance width-to- length ratio to maintain power dissipation at a low level. At this point in time (standby), the only remaining current flow in the circuit is through devices T7 and T8. But the gate potential at T7 and T8 is adjusted (as described above) to maintain these devices only partially on, thereby dissipating relatively little power.

Next, the BOOST input is raised slightly, while nodes PC and R1 are brought to a down level. The result is that nodes A and B charge to a voltage just below +V, and node NI remains at +V-Vt. Devices T9 and T10 have a width-to-length ratio that is many times larger than T7 and T8 so that nodes C and D rem...