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Bipolar Random Access Memory Cell With Bilateral NPN Bit Line Coupling Transistors

IP.com Disclosure Number: IPCOM000089090D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 74K

Publishing Venue

IBM

Related People

Cavaliere, JR: AUTHOR [+2]

Abstract

This is a bipolar random-access memory cell with the advantages of low current and voltage operation without sacrificing performance.

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Bipolar Random Access Memory Cell With Bilateral NPN Bit Line Coupling Transistors

This is a bipolar random-access memory cell with the advantages of low current and voltage operation without sacrificing performance.

Referring now to Fig. 1, there is shown a storage cell including cross-coupled NPN transistors T1 and T2 having PNP load devices T5 and T6. The emitters of the PNP load devices are connected to the PNP emitter bus VP, while the base electrodes of T5 and T6 are connected to the PNP base bus VN. NPN transistor T3 has its emitter connected to the left storage node VL, its base connected to the word line WL and its collector connected to the left bit line VBL. Transistor T4 is similarly connected to the right storage node VR, the word line WL, and the right bit line VBR. The emitters of T1 and T2 are connected to the cell bottom line VB. Both T1 and T2 have base-to-collector Schottky barrier diodes, as shown.

In order to describe the operation of the cell, the three modes (standby mode, read mode, write mode) are described separately. First, for the standby mode, assume that the cell bottom line VB is at zero volts, the word line WL is at .5 volt, and the bit lines VBL and VBR are at 1.5 volts. Further, assume that the PNP emitter bus VP is at 1.5 volts, the base bus VN is at 0.7 volt, the left storage node VL is at 0.2 volt and the right storage node VR is at 0.8 volt. Under these conditions, T1 is on while T2 is off. The sum of the collector currents through PNP transistors T5 and T6 is the cell standby current. This current flows out the emitter of T1 into the cell bottom line. For storage of the opposite polarity data, T1 would be off and T2 would be on, VL would be 0.8 volt, and VR would be 0.2 volt. In either case no current flows through T3 and T4.

Next, the read mode is described. In order to read from the Fig. 1 cell, all voltages are as in the standby mode except that the word line voltage WL is raised to 1 volt. Assume that T1 is on and T2 is off. The emitter-base junction of T3 becomes forward-biased, causing it to conduct. Also, the emitter-base junction of T4 is insufficiently forward-biased (0.2 volt) for conduction. A current- sensing circuit detects the difference between the bit line current through T3 and T4. In the read mode, the cell current is the sum of the emitter current of T3 and the two PNP collector currents. This current flows out the emitter of T1 and into the cell bottom line. Therefore, to prevent disturbing the state of the cell, the value of the emitter current of T3 must be limited to a value supportable by the base current of T1.

Next, the write mode is described. In the write mode, all voltages are the same as in the standby mode except the word line WL is again raised to 1 volt as in the read mode, and, also, the right bit line VBR is lowered to 0.2 volt. The collector-base junction of T4 is then forward-biased, causing a current to flow into the right bit line. Assuming that T1 was i...