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Decoder for Ground Up Array With STL Compatible Output

IP.com Disclosure Number: IPCOM000089091D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Varadarajan, HD: AUTHOR

Abstract

Ground-down random-access memories (i.e., random-access memories using negative supplies, e.g., -4.25V, -1.5V) may be designed using a bipolar multiemitter memory cell (Fig. 1A). Output logic levels around -1.5V may be easily generated. However, employing the same memory cell for a ground-up (using positive supplies of +SV, +1.65V) design needs differently optimized peripheral circuits. Thus, the circuit of Fig. 1B finds difficulty in generating TTL (transistor-transistor logic) or STL (Schottky transistor logic) levels because the cell operates close to the +5V (10%), while the logic output is related to ground. Typical problems are imperfect turn-off of the output Tx T5 or saturation of the sense amplifier device T3.

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Decoder for Ground Up Array With STL Compatible Output

Ground-down random-access memories (i.e., random-access memories using negative supplies, e.g., -4.25V, -1.5V) may be designed using a bipolar multiemitter memory cell (Fig. 1A). Output logic levels around -1.5V may be easily generated. However, employing the same memory cell for a ground-up (using positive supplies of +SV, +1.65V) design needs differently optimized peripheral circuits. Thus, the circuit of Fig. 1B finds difficulty in generating TTL (transistor-transistor logic) or STL (Schottky transistor logic) levels because the cell operates close to the +5V (10%), while the logic output is related to ground. Typical problems are imperfect turn-off of the output Tx T5 or saturation of the sense amplifier device T3.

The present solution was found after various attempts to solve the problem. The memory cell is operated about 2.6V below the +5V. This provides a larger swing at the sense amplifier output without saturation and also enables a translation circuit to be designed (Fig. 2). In this design R1 drops about 1.8V in each word.

Note that Q1 of the eight circuits in the array decoders are all tied together. This is done to reduce individual word line potential variations as also to use point Q1 to generate the read reference for the sense amplifier. Resistor R2 and diode D1 ensure that the Up and Down levels of the words differ by one Vbe. T1 (Fig. 2) is included to buffer the word driver Tx, thus reduci...