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Electrically Hazard Free Latch Circuit

IP.com Disclosure Number: IPCOM000089097D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Eichelberger, EB: AUTHOR [+3]

Abstract

A problem encountered in polarity-hold latch designs implemented in DTL (diode transistor logic) is that a glitch, which can propagate through subsequent stages of logic, appears at the output(s) of the latch upon clocking the latch to a "Set" condition. This situation will occur when the latch having been clocked to a "Set" condition, is subsequently clocked with the "Set" condition still present. The inherent skew in the complementary clock inputs to the latch is the cause of this condition. This clock skew causes the latch to tend to reset before the new set condition can be gated into the latch.

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Electrically Hazard Free Latch Circuit

A problem encountered in polarity-hold latch designs implemented in DTL (diode transistor logic) is that a glitch, which can propagate through subsequent stages of logic, appears at the output(s) of the latch upon clocking the latch to a "Set" condition. This situation will occur when the latch having been clocked to a "Set" condition, is subsequently clocked with the "Set" condition still present. The inherent skew in the complementary clock inputs to the latch is the cause of this condition. This clock skew causes the latch to tend to reset before the new set condition can be gated into the latch.

The glitches described above make the measurement of delays through logic paths on LSI (large-scale integration) chips impossible due to the unpredictable nature of the propagation of these glitches through the logic.

Figs. 1A, 1B and 2A, 2B show a clock driver and polarity-hold latch implementation. Figs. 1A, 1B show how the complementary clock signals are generated. The function of the first circuit 1 of the clock driver is to accept the clock signal (either from on or off chip) and to allow appropriate logical gating of the clock. The second circuit 2 provides the complementary phase of the clock. The switching threshold of the second circuit is approximately 500 mV higher than the threshold of the first stage 3 (Fig. 2A) of the latch. In the past, the higher switching threshold of the second gate 2 (Fig. 1A) of the clock driv...