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Dynamic Bandwidth Variation in Digital Timed Filters

IP.com Disclosure Number: IPCOM000089107D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Maddens, F: AUTHOR

Abstract

This is a fully recursive digital filter provided with means for updating the data stored in its shift register whenever its bandwidth is adjusted.

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Dynamic Bandwidth Variation in Digital Timed Filters

This is a fully recursive digital filter provided with means for updating the data stored in its shift register whenever its bandwidth is adjusted.

The filter comprises an input IN, an adder omega, a shift register T1, T2 and two multipliers 1l, M2. The filter bandwidth is directly related to the values of weighting coefficients applied to the second inputs of amplifiers M1 and M2. Let us first assume that these coefficients are equal to a/1/(1) and a/1/(2), respectively, with the filter being then tuned to

The filter bandwidth may be adjusted to its second shape by just changing the coefficients a/1/(1) and a/1/(2) to precomputed values a/2/81) and a/2/(2) However, due to the incidence of the contents of T1 and T2 on the filter output, the bandwidth adjustment will go through a transient situation for several runs, unless these register contents are changed just before switching to the new coefficient values.

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The component couples (R(1),I(1)) and (R(2),I(2)) may be stored in a ROS memory, the output of which is connected to a circuit designated as ROT in the figure. The output of T(1) is added to the output of R of a second couple of values to be fed to ROT. The second input of this couple is designated by I, and is fed from the output of T(2) and multiplied by sin alpha.

The filter being tuned on its first bandwidth, i.e., coefficients a/1/(1), a/1/(2), the device ROT will start operating and...