Browse Prior Art Database

High Speed, High Level Signal Driver

IP.com Disclosure Number: IPCOM000089129D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Bula, J: AUTHOR [+3]

Abstract

A low level signal is translated into a high level signal with a minimum propagation delay time by the circuit disclosed herein.

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High Speed, High Level Signal Driver

A low level signal is translated into a high level signal with a minimum propagation delay time by the circuit disclosed herein.

Transistors T1, T2 and T3 are enhancement-mode devices. Transistors T4, T5 and T6 are depletion-mode devices. A low level signal is applied to the node A, which will generate a high level signal at the output node D in the minimum propagation delay time. When the input A is in a down level, the output D will be set to the down level. The device T4 provides a high voltage drive at the gate of device T2 and T3. Device T5 provides a high voltage drive at the gate of the device T6. The output D is capable of driving a high capacitive load.

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