Browse Prior Art Database

Interlaced Raster Scan Display

IP.com Disclosure Number: IPCOM000089146D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Nicholson, LW: AUTHOR

Abstract

The above block diagram shows the operation of the raster-data synchronization circuitry for an interlaced scan raster display.

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Interlaced Raster Scan Display

The above block diagram shows the operation of the raster-data synchronization circuitry for an interlaced scan raster display.

The basic input from which the timing circuitry generates all synchronizing signals is the input clock signal on line 3, each cycle of which represents a "dot" time. In the environment of a 10 X 24 character position matrix, this signal is fed to a divide-by-10 circuit 4 which develops the basic character timing, different phases being used to clock the row buffer and character/attribute circuits and the character generator read-only storage (ROS). A gated version of the input clock signal on line 6 shifts the video serializer. One of the phases of the character timing, divide-by-10 circuit 4 on line 7 is used to increment column counter 8. Counter 8 produces horizontal scan timing, such as horizontal drive sync on line 9 and row buffer address counter sync on line 10, which insures synchronization between the characters in a horizontal scan and the horizontal beam movement. Counter 8 also produces a "half scan signal" on line 11 which is used to increment vertical drive counter 13.

The interlaced scan function is a result of this half-scan counting. That is, the vertical drive counter 13 counts an odd number of half-scans to produce a vertical drive sync signal. In this way scan interlacing is achieved by causing the scans of each vertical sweep to fall midway between the scans of the preceding vertical sweep. The v...