Browse Prior Art Database

Address Controlled Clocking of Recirculating Memories

IP.com Disclosure Number: IPCOM000089155D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 106K

Publishing Venue

IBM

Related People

Handloff, LE: AUTHOR

Abstract

This article describes a method and apparatus for reducing average access time of recirculating memories, such as of the charge-coupled device (CCD) type, by logic control of clock frequency.

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Address Controlled Clocking of Recirculating Memories

This article describes a method and apparatus for reducing average access time of recirculating memories, such as of the charge-coupled device (CCD) type, by logic control of clock frequency.

Fast and slow clock frequencies are employed. Briefly, once past the desired address, the recirculation rate of the CCD is increased. Then, it is reduced as the desired address is approached, in order to maximize the period during which the access time will be small. When an access request demand is received, the rate is again increased to the maximum to get to the desired address with minimum access time.

For the conventional CCD (Fig. 1a) recirculating at its maximum speed, the average access time is the area OPQ under the access time curve PQ divided by the period OP. The average access time equals one-half the period P.

With clock speed control, however, the average access time is minimized (Figs. 1b and 2). The ratio of maximum to minimum clock speed, M, is maximized and for every M, there is an optimum N, the portion of the total CCD period using the faster clock frequency. The CCD runs at maximum speed for a time NxP denoted by OA; then at A it switches to the slower speed. The remaining time period is thus increased significantly from AP to AP', extending the total period greatly (i.e., from OP to OP'), while the total area under the access time curve is increased by a smaller proportion (i.e., from OQBP to OQBP'). Thus, AT(AV) = 1/2 (fast period, OP)(1-(1-N)/2/ (1-N)/2/ divided by M) over N (1-N) divided by M). The optimum value of N can be found by differentiation.

Apparatus to implement this method is shown in Fig. 3. Master scheduler 1 (e.g., a microprogram) could make starting address assignments to several independently controlled buffer arrays. Each array 2 requires an address counter 3 that always shows the instantaneous memory address; a displa...