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Compression of Silence in Digitized Speech Recording

IP.com Disclosure Number: IPCOM000089158D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Patten, MA: AUTHOR

Abstract

This silence data compression arrangement reduces the storage requirement with low outlay for components.

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Compression of Silence in Digitized Speech Recording

This silence data compression arrangement reduces the storage requirement with low outlay for components.

Voice frequency waves to be recorded in digital form are are applied at input terminals 10 (Fig. 1). A clocking pulse wave is applied at terminals 12. These waves are translated in a delta modulator circuit 14 which delivers a binary 1 or phi output corresponding to an increase or decrease in the amplitude of the voice wave and alternate 1 and phi signifying no changes in amplitude.

The serial data output from the delta modulator 14 is applied to a deserializing circuit 16 from which 16-bit data is presented to a register 18. This register is loaded at the end of each word of 16 bits. The words are separated by the action of logic circuit arrangement 20 which generates a service request. The word in the register 1a is then transferred through a selector circuit 24 to the output lines. An electric level applied at an input terminal 22 indicates a response from the system that the data has been received.

If the output of the delta modulator 14 is a "silence" word, the pattern will be alternate 1 and phi. A "silence" detector 26 will increment a counter 28 for translating a 16-bit "silence word" to the selector 24, and at the completion of the count, the selector 24 is switched and the "silence word" is transferred to the output lines for storage.

For reproduction the output of the selector 24, as recorded, is delivered to a register decrementer 40 (Fig. 2). A clock pulse wave is applied at an input terminal 42 for timing a serializer circuit 44 and a silence word detecting circuit
46. As before, the detecting circuit 46 is also given an end-of-word pulse from a data service request logic circuit 50. The detecting circuit 46 supplies an electric level, indicating a "silence word detected", to the logic circuit 50, and selects the output of a divider circuit 52 for application through a selector circuit 54.

In operation "silence" is compressed by detecting a word of silence (alternate 1 and phi) coming from the delta modulator and allowing this word to be stored normally. A count is then made of subsequent silence words. During the counting no words are stored. When the first non-silence word is detected, a storage cycle is initiated and the count is stored just following the first silence word which was stored. If the nonsilence word just detected is completely deserialized before the count storage cycle is complete the request for this word is queued and presented immediately following the count storage cycle. Deserializing and storing of subsequent nonsilence words proceeds normally until the next group of silence words or the end of the operation.

If the word following the first silence word is a nonsilenc...