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DMOS FET With Common Field and Channel Doping

IP.com Disclosure Number: IPCOM000089181D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 79K

Publishing Venue

IBM

Related People

Crowder, BL: AUTHOR [+2]

Abstract

This article describes how the short channel doping and the field doping may be combined to reduce processing steps in a DMOS FET (double-diffused metal-oxide-silicon field-effect transistor). A drain side blocking mask, rather than a source side window opening, is used for the common channel/field boron implantation. Due to the asymmetrical channel doping, the DMOS FEI offers improved performance over a conventional NMOS FET (n-channel MOS FET) having the same source-to-drain spacing. These two devices are shown in Figs. 1A and 1B. Compared to an NMOS device, a DMOS device requires an additional masking step to provide the p-type doping for the short channel (injection region) on the source side of the device. An additional diffusion step is also required.

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DMOS FET With Common Field and Channel Doping

This article describes how the short channel doping and the field doping may be combined to reduce processing steps in a DMOS FET (double-diffused metal- oxide-silicon field-effect transistor). A drain side blocking mask, rather than a source side window opening, is used for the common channel/field boron implantation. Due to the asymmetrical channel doping, the DMOS FEI offers improved performance over a conventional NMOS FET (n-channel MOS FET) having the same source-to-drain spacing. These two devices are shown in Figs. 1A and 1B. Compared to an NMOS device, a DMOS device requires an additional masking step to provide the p-type doping for the short channel (injection region) on the source side of the device. An additional diffusion step is also required. Described here is a novel means for fabricating DMOS devices in which the p-type short channel doping under the gate oxide and the p-type field doping under the field isolation oxide are provided in the same step, thereby simplifying the process.

Two processing approaches are described. In the first one, the gate pattern is defined before the field pattern. Then a self-registering contact [*] can be used over the gate. This is not required but is advantageous because the polysilicon layer cannot be used for interconnections. Processing simplicity is the primary attraction of this approach.

A second and slightly more complicated approach is described which facilitates the fabrication of depletion-mode devices. Here the field pattern precedes the gate pattern. The initial field oxide thickness must be small enough so that the boron implantation can penetrate through to the field region. Again, a self-registering gate contact can be employed, if desired.

Fig. 2 shows side and top views of the DMOS structure fabricated using the simpler common channel/field process. The first step of the process is to grow the gate oxide of 500 angstroms thickness over the entire wafer. Then a CVD (chemical vapor deposition) polysilicon layer is deposited, doped n+, and an oxidation barrier layer (silicon nitride) is deposited over the polysilicon. Thin oxide layers may be used on either side of the nitride layer to aid in its delineation and removal. Now one etches down through the oxidation barrier and polysilicon to define the gate pattern.

The next step is to define a resist region to block p-type channel/ field doping on the drain side of the device (Fig. 2A). This is in contrast to other DMOS fabrication procedures in which an opening is commonly provided on the source side to obtain the DMOS channel doping. With the new approach the p-type doping will occur everywhere except on the drain side of the device and directly under the polysilicon gate. The polysilicon is typically 3500 A thick and the nitride layer 500 angstroms thick. Now the drain-side resist block is removed by dissolving. Next, the field isolation oxide is grown about 3000 angstro...