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Single Counter Controlled Buffer

IP.com Disclosure Number: IPCOM000089218D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Dunn, EC: AUTHOR [+2]

Abstract

Data signal processing devices such as error correction systems in data recording channels often require buffering of syndrome signals, data signals, error location signals, and the like. In such apparatus an input data system operates synchronously with an output data system under control of a single clock. A simple control can sequence the operation of the various parts including a buffer random access memory. The random-access memory is accessed in a processing manner as indicated in the flow chart. A MOD 2 counter K alternately actuates the illustrated AND circuits for connecting the random access memory to the two data systems. The address counter is, in turn, incremented by the MOD 2 counter. Actually the MOD 2 counter can be the least significant digit position of the address counter.

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Single Counter Controlled Buffer

Data signal processing devices such as error correction systems in data recording channels often require buffering of syndrome signals, data signals, error location signals, and the like.

In such apparatus an input data system operates synchronously with an output data system under control of a single clock. A simple control can sequence the operation of the various parts including a buffer random access memory. The random-access memory is accessed in a processing manner as indicated in the flow chart. A MOD 2 counter K alternately actuates the illustrated AND circuits for connecting the random access memory to the two data systems. The address counter is, in turn, incremented by the MOD 2 counter. Actually the MOD 2 counter can be the least significant digit position of the address counter.

After the random access memory is initially loaded with data signals, register #1 of the random access memory is first read out. The clock toggles the MOD 2 counter and the input data system supplies a replacement set of data signals to position #1. The address counter responds to the change in the MOD 2 counter to increment the address after the write-in process. Then the register #2 is read out, written in, and the address counter incremented. The process is continuously repeated for scanning the registers of the random access memory in a read/write mode for effectively providing a delay and storage between the input data system and the outp...