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Floating Point Multiply Divide Assist

IP.com Disclosure Number: IPCOM000089234D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Jeremiah, TL: AUTHOR [+2]

Abstract

In floating point (FP) multiply and divide, the computation of result sign and characteristics, as well as testing for underflow, overflow, and nonnormalized data, is time consuming. These minor operations occupy a significant part of the total time of floating point multiply and, to a lesser extent, floating point divide.

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Floating Point Multiply Divide Assist

In floating point (FP) multiply and divide, the computation of result sign and characteristics, as well as testing for underflow, overflow, and nonnormalized data, is time consuming. These minor operations occupy a significant part of the total time of floating point multiply and, to a lesser extent, floating point divide.

However, by incorporating hardware assist, these steps can be accomplished concurrently under the control of one microword, which uses a branch format to facilitate control store module switching. Module switching is usually required because of the size of multiply and divide programs.

The hardware assist for floating point multiply and divide can be implemented within the 8-byte main dataflow of a large computer. It consists of a small number of circuits located mainly in the Arithmetic Logic Unit (ALU). The figure shows a block diagram of the major parts of the dataflow. Local Storage contains general purpose registers, floating point registers, and working registers. The B Register is used to latch the output of local storage, while the A Register acts as an accumulator register. The output of the ALU is temporarily latched in the Destination Register before being stored away in Local Storage or the A Register. Control Storage contains the microprogram, which is executed from the Control Register.

Operand 1 is loaded into the A Register prior to execution of the FP microinstruction. The A Register byte 0 contains the sign and characteristic of operand 1. Bytes 1-7 contain fraction digits. Execution of the FP microinstruction causes operand 2 to be loaded into the B Register from the floating point register located in Local Storage. B Register byte 0 then contains the sign and characteristic of operand 2. Bytes 1-7 contain fraction digits. At this point, a simple hardware test is made to determine whether either fraction is nonnormalized. If a zero hexadecimal digit is detected in either register in the left most digit of byte 1, then a branch addres...