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Darlington Current Sink

IP.com Disclosure Number: IPCOM000089257D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Montegari, F: AUTHOR

Abstract

The high speed OR INVERT logic circuit depicted in the figure features high impedance inputs for minimum loading of the driving circuit.

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Darlington Current Sink

The high speed OR INVERT logic circuit depicted in the figure features high impedance inputs for minimum loading of the driving circuit.

When all inputs (A, B and C) are at a down level, current from R2 flows into the base of T4 and through saturation clamp D1 into the collector of T4. The current then flows through R1 to -VEE, producing a level at node E which turns T5 off. When any input (A, B or C) is at an up level, D1 is reverse biased, and the emitter and base of T4 are pulled more positive by the T4 collector current supplied through the emitter of whichever one of the transistor(s) T1-T3 is on, thereby leaving a small base current flowing from R2 into the base of T4. The remainder of the current through R2 turns T5 on, with any excess being shunted through saturation clamp D2.

Circuit components D1, T4, R1 and R2 perform the dual function of current sink and coupling device. Transistor T4 acts as a constant current sink whose collector current requirement must be satisfied through the emitter of one or more of the transistors T1-T3 when an input (A, B, or C) is at an up level, or by means of a current path through R2, D1 when all inputs (A, B or C) are down. Maximum T1-T3 emitter current is limited by the constant current design value controlled by R1. Resistor R2 supplies base drive to T4 or to both T4 and T5 depending on the state of the circuit inputs. The input terminal D illustrates a provision for an emitter-follower input. T...