Browse Prior Art Database

ALU Fault Detection

IP.com Disclosure Number: IPCOM000089264D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Cheng, GT: AUTHOR

Abstract

Arithmetic logic units (ALUs) commonly include a complete parity prediction scheme which gives a very high degree of checking but at the expense of high circuit count. For many applications this is not necessary. An effective, while inexpensive, ALU checking technique is shown in the figure, in which the ALU is not checked during an actual operation but is checked at all other times. The checking is accomplished by executing a known operation on known inputs and comparing the actual result with the expected result.

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ALU Fault Detection

Arithmetic logic units (ALUs) commonly include a complete parity prediction scheme which gives a very high degree of checking but at the expense of high circuit count. For many applications this is not necessary. An effective, while inexpensive, ALU checking technique is shown in the figure, in which the ALU is not checked during an actual operation but is checked at all other times. The checking is accomplished by executing a known operation on known inputs and comparing the actual result with the expected result.

The exercise of the ALU circuitry is performed under hardware control when the ALU is idle otherwise. For instance, in an ALU operation involving two operands, as depicted in the figure, the ALU is idle during loading into the register of the first operand. Constant values are gated to the ALU, and the result checked for correctness at this time (i.e., simultaneously with the loading of the first operand), to be followed by gating the second operand to the ALU for the actually intended ALU operation. Thus, the ALU circuitry is checked within microseconds of its actual usage, well within the duration of most transient errors.

Constants of uniform bit patterns are effective for checking the ALU. For example (assuming a 4-bit ALU for illustration): (a) `1111' + `1111' + carry-in = `1111' with carry-out check some stuck-at-zero faults in the `sum' and `carry' circuitry of the adder. (b) `0000' + `0000' = `0000' without carry-out check s...