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Random Access Memory Buffer for Bidirectional Serial Printer

IP.com Disclosure Number: IPCOM000089275D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Kohsaka, Y: AUTHOR [+2]

Abstract

Dot matrix patterns are supplied to a random-access memory 3 for operation of bidirectional wire matrix printer 7. Storing and reading operations of memory 3 are concurrently performed under control of reversible pointers 1 and 2, whereby matrix patterns, supplied from character generator 4 in one direction, are bidirectionally entered into and read out of memory 3 so as to conform to the bidirectional motion of the print head.

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Random Access Memory Buffer for Bidirectional Serial Printer

Dot matrix patterns are supplied to a random-access memory 3 for operation of bidirectional wire matrix printer 7. Storing and reading operations of memory 3 are concurrently performed under control of reversible pointers 1 and 2, whereby matrix patterns, supplied from character generator 4 in one direction, are bidirectionally entered into and read out of memory 3 so as to conform to the bidirectional motion of the print head.

Generator 4 is arranged to provide matrix patterns through sequential generation of columns of dots in one direction, which is equivalent to the left-to- right direction along each print line. In order to enable bidirectional printing by making use of such generator 4, a pair of reversible pointers 1 and 2, which operate as up-down address counters, are provided for concurrently accessing two storage areas of memory 3.

The pointer arrangement in Fig. 1 has two operating modes, namely mode 0 and mode 1. In mode 0, pointers 1 and 2 are concurrently incremented on the basis of a byte. During this mode, matrix patterns for one print line, already stored in one storage area, are sequentially read out by incrementing pointer 2 while, at the same time, matrix patterns for the next print line, coming from generator 4, are sequentially stored in another storage area by incrementing pointer 1. In mode 1, pointers 1 and 2 are concurrently decremented, and the roles of the pointers are interchanged with each other.

The system in Fig. 1 proceeds in phases 0 thru 8, but these phases can be defined by modes 0 and 1, respectively. Referring to Fig. 2 and the...