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Testing Multispeed LSI Chips

IP.com Disclosure Number: IPCOM000089276D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Mitchell, RC: AUTHOR

Abstract

With the advancement of large-scale integration (LSI) and system design, there are requirements for different speed logic on the same chip. These different sections (macros) of logic (single, double, triple speed, etc.) have their own clocks when in the machine (i.e., single, double, triple speed clocks). It is desired to be able to test these different speed logic macros in the level sensitive scan design test philosophy. The characteristics of the chip design and test methods are described more fully in U. S. Patents 3,806,891 and 3,783,254.

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Testing Multispeed LSI Chips

With the advancement of large-scale integration (LSI) and system design, there are requirements for different speed logic on the same chip. These different sections (macros) of logic (single, double, triple speed, etc.) have their own clocks when in the machine (i.e., single, double, triple speed clocks). It is desired to be able to test these different speed logic macros in the level sensitive scan design test philosophy. The characteristics of the chip design and test methods are described more fully in U. S. Patents 3,806,891 and 3,783,254.

A method to accomplish this is to test all logic at the speed of the slowest macro. This is done by providing external connections, whereby in the tester the higher speed clock pins are connected to a clock or clocks having pulse characteristics of the higher speed clock(s) but repetitive at the same rate as the slowest speed clock.

The LSI chip shown in Fig. 1 contains two logic sections which operate at different frequencies. The double speed logic section 10 uses the single speed clock f as a logic signal. A physical path is built into the chip to allow a separate entry point 12 for f clock's usage as a logic signal to the double speed logic section. Input 14 is the entry point for f clock's usage as the single speed logic clock in single speed logic 16.

In Fig. 1 where the chip is in the machine an external jumper 18 connects input 12 to f clock. The double speed clock 2f required for operat...