Browse Prior Art Database

Ramped Write and Erase Pulses for Gas Panel Tester

IP.com Disclosure Number: IPCOM000089294D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Carlo, A: AUTHOR

Abstract

The tester for gas panel display described in [*] utilizes ramped write and erase pulses which may be generated by the circuit shown above.

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Ramped Write and Erase Pulses for Gas Panel Tester

The tester for gas panel display described in [*] utilizes ramped write and erase pulses which may be generated by the circuit shown above.

The logic gate for the horizontal side comprises NAND blocks 1, 2, 3, 4, 6 and 7, and for the vertical side it comprises blocks 11, 12, 13, 14, 16 and 17. The entire logic network for the horizontal side is made up of blocks 1 through
10. Conversely the vertical side is made up of blocks 11 through 20. Blocks 1A and 2A are inverters.

A standard high voltage drive circuit is composed of Darlington pairs Q7, Q8; Q12, Q13; Q5, Q6; Q14, Q15 and the low voltage drivers Q11, Q16 with their respective pulse transformers T4 and T3. This modified circuit includes Darlington pairs Q9, Q10 and Q3, Q4; low voltage drivers Q1, Q2; pulse transformers T1 and T2; and high voltage blocking diodes D1, D2 and D3.

The circuit is normally fed by a two-phase clock at points X and Y. Clock X turns on Darlington pairs Q12, Q13 with the drive from Q11 and pulse transformer T3. Simultaneously, Q8 and Q9 are also turned on by T3. This places point A at nominal ground and point D at +HVS (high voltage sustain). With the input of Q2 at Y, D now goes to ground while A goes to +HVS. Every alternate input from X and Y flips A and D around.

With the introduction of a gating network and the additional driver parts we can now increase the amplitude of the pulse or delete it entirely as follows. The introductio...