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Motor Control for Acceleration and Deceleration by Variable Rate Pulses

IP.com Disclosure Number: IPCOM000089297D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Kent, EM: AUTHOR

Abstract

The above circuit receives clock pulses at a fixed rate on line 2, and supplies pulses at a selected rate to a control 4 for a direct current motor 5. When a signal on line 6 rises (RUN), pulses are supplied at an increasing rate until the clock rate is reached for maximum motor speed. When the signal on line 6 falls (STOP), the pulses are supplied for a short time at a decreasing rate to decelerate the motor.

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Motor Control for Acceleration and Deceleration by Variable Rate Pulses

The above circuit receives clock pulses at a fixed rate on line 2, and supplies pulses at a selected rate to a control 4 for a direct current motor 5. When a signal on line 6 rises (RUN), pulses are supplied at an increasing rate until the clock rate is reached for maximum motor speed. When the signal on line 6 falls (STOP), the pulses are supplied for a short time at a decreasing rate to decelerate the motor.

Two single-shot circuits 8 and 9 respond to the rise and fall, respectively, of the signal on line 6 to produce pulses for setting a latch 12 and for initializing other components of the circuit. When latch 12 is set, it enables gates 14 and 15 to transmit clock pulses that are supplied at a variable rate on line 16. When the latch is reset after acceleration, it controls gates 15 and 17 to transmit clock pulses at the fixed clock rate.

A cascade connection 20 of two synchronous decade rate multipliers receives the clock pulses on line 2 and produces the variable rate pulses on line 16 according to an input from a cascade connection 25 of two decade counters. These circuits are standard components. To begin acceleration, the counter circuit is set to 00, and it is incremented by one for each 100 clock pulses by a signal on line 26 from the rate multiplier circuit. Thus, during successive sequences of 100 clock pulses, the counter circuit 25 counts from 00 to 99, and on each of these cyc...