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Majority Decoding of the (17,9) Quadratic Residue Code

IP.com Disclosure Number: IPCOM000089302D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

A majority logic decoding scheme is described for the (17,9) quadratic residue binary code with the parity check matrix defined by H == [I(8) P], where (Image Omitted) Let R be a received code vector, and h be a vector in the row space of H. The dot product R h is called a check sum. The code positions are numbered 16,15,....,1,0. For example, let h = 00000011010001011. R(10) + R(9) + R(7) + R(3) + R(1) + R(0) is a check sum. This check sum is represented by (10, 9, 7, 3, 1, 0).

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Majority Decoding of the (17,9) Quadratic Residue Code

A majority logic decoding scheme is described for the (17,9) quadratic residue binary code with the parity check matrix defined by H == [I(8) P], where

(Image Omitted)

Let R be a received code vector, and h be a vector in the row space of H. The dot product R h is called a check sum. The code positions are numbered 16,15,....,1,0. For example, let h = 00000011010001011. R(10) + R(9) + R(7) + R(3) + R(1) + R(0) is a check sum. This check sum is represented by (10, 9, 7, 3, 1, 0).

Let E(i) be the error value at position i. The following set of 16 check sums is used to estimate E(o).

(Image Omitted)

The value of E(o) is set to zero, if 8 or less number of the check sums are 1; the value of E(o) is set to one, if more than 8 of the check sums are 1. A majority logic gate is used to implement the decision rule.

Since this code is cyclic, the value of E(i) for 1 </= i </= 8 can be estimated by cyclic shifting of the received code word with the same majority logic gate.

A block diagram of the decoder is shown in Fig. 1. The decoder is operated as follows: 1. With switch S(1) closed and switch S(2) open, a block of 17-bit received code vector is shifted into the 17-stage shift register. 2. With switch S(1) open and switch S(2) closed, data bits are corrected and shifted out one bit at a time.

The Exclusive OR tree generates 16 outputs corresponding to the set of 16 check sums listed above. The outputs are fed into th...