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Circuit Module Interconnecting Testing

IP.com Disclosure Number: IPCOM000089360D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Hack, GE: AUTHOR

Abstract

The emitter terminals of representative transistors 2 and 3 are conventionally connected to output pins 4 and 5 respectively, of a circuit module or chip. The other terminals of transistors 2 and 3 are connected to points of operating potential or signal potential in the module. Pins 4 and 5 of the module of the drawing may be connected to input pins of other modules in a multimodule circuit device. In one test for the continuity of the wiring that interconnects these modules, a voltage is applied to pins 4 and 5 of the module of the drawing and the voltage at an input pin of another module is tested. The wiring between the two modules is satisfactory if the voltage appears at both pins.

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Circuit Module Interconnecting Testing

The emitter terminals of representative transistors 2 and 3 are conventionally connected to output pins 4 and 5 respectively, of a circuit module or chip. The other terminals of transistors 2 and 3 are connected to points of operating potential or signal potential in the module. Pins 4 and 5 of the module of the drawing may be connected to input pins of other modules in a multimodule circuit device. In one test for the continuity of the wiring that interconnects these modules, a voltage is applied to pins 4 and 5 of the module of the drawing and the voltage at an input pin of another module is tested. The wiring between the two modules is satisfactory if the voltage appears at both pins.

In this module, additional driver transistors 7 and 8 have their emitter terminals connected to module pins 4 and 5 in parallel with a related driver 2 or
3. The collector terminals of transistors 7 and 8 are connected to a suitable point of potential on the module and their base terminals are connected in common to an input pin 9 of the module for receiving a test signal. When the test signal at pin 9 rises, drivers 7 and 8 turn on to apply an output voltage to output pins 4 and 5 of the module for the continuity test. This test circuit can alternatively be formed by diodes connected between the test signal input pin 9 and the individual output pins.

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