Browse Prior Art Database

Niobium Tunnel Junction Fabrication

IP.com Disclosure Number: IPCOM000089373D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Broom, RF: AUTHOR

Abstract

The drawings depict the process steps. The bottom line M2 of the junction is arranged on a substrate which is not shown. The junction area is masked, and oxide 12 is deposited. Without removing the masking stencil, a film of easily etchable metal, semiconductor or dielectric is deposited to a thickness of about 1000 Angstroms. Suitable materials are, e.g., Al, Cu or Si. The result, after removal of the stencil, is shown in Fig. 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Niobium Tunnel Junction Fabrication

The drawings depict the process steps. The bottom line M2 of the junction is arranged on a substrate which is not shown. The junction area is masked, and oxide 12 is deposited. Without removing the masking stencil, a film of easily etchable metal, semiconductor or dielectric is deposited to a thickness of about 1000 Angstroms. Suitable materials are, e.g., Al, Cu or Si. The result, after removal of the stencil, is shown in Fig. 1.

A resist stencil is next applied around the junctions. This can be a simple mask having windows larger than those in the 12 layer, e.g., the mask used later to define M3. Registration and tolerances need only be sufficient to limit the films to within the areas covered by 12. The junction base electrodes M2a are next deposited, followed by oxidation to form the tunnel barrier, and finally the top electrode M3a is deposited. A cross section of the structure after completion of the junction is shown in Fig. 2. The only restriction at this stage is that the oxide thickness plus coating be greater than the combined thickness of M2a and M3a. After stripping the resist, the wafer is subjected to an acid etch to remove the coating, along with the M2a and M3a films lying on the oxide. The devices are then completed by the addition of M3 (Fig. 3).

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]