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Rectilinear Vector Generation

IP.com Disclosure Number: IPCOM000089381D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Rowe, HL: AUTHOR

Abstract

The generation of rectilinear vectors is described for storage in a 16-bit word-organized store. Vectors may have any origin, length or direction.

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Rectilinear Vector Generation

The generation of rectilinear vectors is described for storage in a 16-bit word-organized store. Vectors may have any origin, length or direction.

The storage is an image of a display specified by X and Y coordinates, with each bit representing a picture element. Data already in storage must remain intact when a new vector is stored. Thus, vectors must be generated one storage word at a time and stored. The least significant 4 bits of the X coordinate will specify the position of the vector origin within a storage word.

The figure shows the hardware required in block form, the vector latch being set at the beginning of vector generation. Horizontal Vectors.

The decoder positions a "1" from the Vector Latch in the Formation Register, as specified by the C-bit address held in the SB (significant bit) Counter, which is initially set to the 4 least significant bits of the X coordinate. The SB counter is next decremented/incremented according to the Direction Latches being set Left or Right, and the Vector Length in the Length Register is decremented.

Thus, a second "1" is positioned in the Formation Register. These steps are repeated until either the first or last bit of the storage word is reached or the Length Register is "0". A storage word read/ write follows.

Assuming the vector extends into the next storage word, the SB counter is set to 15 for Left-vectors or 0 for Right-vectors, the X address decremented/incremented, and the gene...