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Operational Amplifier Input Stage Biasing Scheme

IP.com Disclosure Number: IPCOM000089384D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Commander, RD: AUTHOR [+2]

Abstract

An operational amplifier input stage biasing scheme is shown in the figure. Input terminals 1 and 2 are connected to the bases of transistors T(1) and T(2), respectively. The emitter/collector paths of T(1) and T(2) are connected in series with the emitter/collector paths of PNP transistors T(3) and T(4) and the emitter/collector paths of transistors T(5) and T(6). Transistor T(7) is biased by a potentiometer chain including diode strapped transistors T(10) and T(11) to perform as a current source and provide the desired currents for T(1),T(2),T(3) and T(4) at its collector.

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Operational Amplifier Input Stage Biasing Scheme

An operational amplifier input stage biasing scheme is shown in the figure. Input terminals 1 and 2 are connected to the bases of transistors T(1) and T(2), respectively. The emitter/collector paths of T(1) and T(2) are connected in series with the emitter/collector paths of PNP transistors T(3) and T(4) and the emitter/collector paths of transistors T(5) and T(6). Transistor T(7) is biased by a potentiometer chain including diode strapped transistors T(10) and T(11) to perform as a current source and provide the desired currents for T(1),T(2),T(3) and T(4) at its collector.

The bias control for T(3) and T(4) is via a feedback loop through grounded base transistor T(9) which provides the base currents for T(3) and T(4). The current through T(3) and T(4) is slightly less than the T(7) collector current, with the remainder of this current flowing through T(9), supplying the value of base current required to support T(3) and T(4) collector currents. If T(3) and T(4) current increases, T(5) and T(6) emitter currents increase, leaving a smaller part of T(7) collector current to provide T(3) and T(4) base current via T(9), tending to turn off T(3) and T(4). Thus this loop has negative feedback.

Output terminal 3 is connected between the emitter of T(14) and the collector of T(8) which shares equally with T(7) the current through the 6 K resistor in the tail. Balancing the input stage to minimize input offsets is achieved...