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Layout Scheme for Large Digital Circuits

IP.com Disclosure Number: IPCOM000089420D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Donath, WE: AUTHOR [+2]

Abstract

This article describes a technique for optimally partitioning Weinberger arrays by breaking the Weinberger image into subunits to provide a higher performance chip with improved layout and design for field-effect transistors. The technique is an extension of the well known Weinberger image [*] and can be described as a coupled Weinberger image.

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Layout Scheme for Large Digital Circuits

This article describes a technique for optimally partitioning Weinberger arrays by breaking the Weinberger image into subunits to provide a higher performance chip with improved layout and design for field-effect transistors. The technique is an extension of the well known Weinberger image [*] and can be described as a coupled Weinberger image.

Essentially, in carrying out the technique, at each stage of the layout process the logic complex is divided into two halves (i.e., approximately two halves, since moderate deviations will not cause a problem), and wiring space is provided between the two circuits, which acts as a cross-point switch, so that each of the two halves can be laid out independently of the other. If n wires communicate between the two halves, about n/2 individual wiring tracks must be provided in the bus, as illustrated in Fig. 1, which shows two coupled Weinberger arrays with interconnection bus. The interconnection wires are typically metal in the vertical direction and diffusions in the horizontal direction. Typically, the bus will have far more tracks than shown in this figure. Power and ground busses are not shown.

Multiple divisions of the logic complex are possible. A 2 x 2 division is shown in Fig. 2, with the main interconnection bus in the vertical direction and two secondary busses in the horizontal direction. Fig. 2 also illustrates the possibility that the four arrays need not be the same size. Power and ground lines are not shown.

There are two methods of estimating the wiring requirements in the busses. If the logic is actually known, then the track requirement can be estimated during the layout process. However, we are interested in a priori sizings of layouts so an estimate is made that the number lines cut by a partition of a lo...