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High Speed, High Sensitivity CCD Comparator

IP.com Disclosure Number: IPCOM000089421D
Original Publication Date: 1977-Oct-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 40K

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Heller, LG: AUTHOR [+3]


A high speed, high sensitivity charge detection structure is described.

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High Speed, High Sensitivity CCD Comparator

A high speed, high sensitivity charge detection structure is described.

Fig. 1 shows a schematic of the charge detection circuit, and its associated timing is shown in Fig. 2. The circuit employs differential sensing. The magnitude of charge quantities Q(1) and Q(2) are to be compared.

During a reset phase, with Phi(0) low, Phi(1) and Phi(2) high, and the gate potentials of devices 2 and 4 each at least one V(T) above ground, nodes 1 and 2 are individually reset to ground potential (through devices not shown). While nodes 1 and 2 are each being reset, the two charge packets Q(1) and Q(2) are each placed into the left and right C:CD (charge-coupled device) wells, respectively.

The N+ diffusions next to the CCD wells have the same surface potential as the well to which they are adjacent. The DC bias on the well electrode and the size of that electrode are such that with the maximum Q(1) and Q(2), the wells can hold the charge completely. Thus, the adjacent diffusions and hence the gates of devices 2 and 4 are at a potential greater than one threshold voltage above ground.

The reset phase ends when Phi(0) rises. Nodes 1 and 2 charge up to one threshold below the gate voltage of devices 2 and 4, respectively (Phi(2) is at a high enough voltage to keep devices 5 and 6 in the linear region). Devices 2 and 4 precharge to cutoff, and the effects of V(T) mismatch are eliminated.

Thereafter, Phi(1) goes low to isolate nodes V(01)...