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Testing Scheme for Programmable Logic Arrays

IP.com Disclosure Number: IPCOM000089450D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Alberts, GS: AUTHOR [+2]

Abstract

In programmable logic array (PLA) architecture the data/logic flow is as follows: a) Data and control fields are fed as inputs into the AND array. b) A match between the inputs and any of the ""n'' product terms is done by a process of association. (The AND array of a PLA is not address decoded like a random-access memory or read-only store. c) The AND terms which match input data activate the OR portions of the same terms. One or more OR terms will respond and emit prestored data into the output lines or into latches to be fed back later into the AND array as one of the input fields.

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Testing Scheme for Programmable Logic Arrays

In programmable logic array (PLA) architecture the data/logic flow is as follows: a) Data and control fields are fed as inputs into the AND array. b) A match between the inputs and any of the ""n'' product terms is done by a process of association. (The AND array of a PLA is not address decoded like a random- access memory or read-only store. c) The AND terms which match input data activate the OR portions of the same terms. One or more OR terms will respond and emit prestored data into the output lines or into latches to be fed back later into the AND array as one of the input fields.

The custom personalization of a PLA is done with masks in one or several process steps. To test for good chips, conventional techniques do not work because the input stimuli may associate with one or many terms. Those terms which respond in the AND array cannot be tapped for verification because the terms are not brought out to external means. This is not done for pin and physical space considerations, and would not contribute to the functionality of the architecture. Rather, the terms feed out of the AND array and into the OR array, which further complicates the testability by ORing all active terms together before emitting the result as output.

To achieve 100% testability, all combinations and permutations of inputs to outputs would have to be exercised. This is prohibitive.

This technique identifies a means for verifying the correctness of responses to any input data after association in the AND array takes place without external means between arrays. This permits a simple sequence of input data to verify the correctness of terms and the response on match conditions.

To shorten and simplify PLA testing, a "sensor" or "detector" is...