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Hall Cell Bias and Offset Circuit

IP.com Disclosure Number: IPCOM000089454D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR

Abstract

The circuit shown above provides the proper bias currents for constant sensitivity and offset compensation of a Hall cell implemented on a bipolar semiconductor chip.

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Hall Cell Bias and Offset Circuit

The circuit shown above provides the proper bias currents for constant sensitivity and offset compensation of a Hall cell implemented on a bipolar semiconductor chip.

The Hall cell 10 consists of an isolated epitaxial pocket with electrodes for a biasing current and voltage sensing. Constant bias current is required for constant sensitivity (input magnetic field, output voltage) at the sense points 11 and 12, or the collectors of transistors T5 and T7. The voltage divider, consisting of diode D1 thru D4 and resistors R1 and R2, attenuates a constant voltage provided by a Zener-type regulator, indicated by Vz. The voltage follower amplifier, consisting of transistors T1, T2, T3, and T4, diode D5 and resistors R3 and R4, holds the voltage across Rs at a constant value. The collector current of transistor T4 is thus held at a value determined by resistor Rs, which is off chip and has a low temperature coefficient. The sensitivity of the Hall cell may then be set to the desired value by selection of Rs, and will not change with temperature.

The offset voltage between points 11 and 12 (voltage across the sense points at zero applied field) is due to dimensional variations in the epi thickness and sense point locations. Since this is a linear resistive material, the offset voltage will be proportional to the applied voltage, which increases as the epi resistivity increases since the bias current is constant. The offset compensation cur...