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Data Processor Fault Analysis Assist

IP.com Disclosure Number: IPCOM000089480D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Cuffaro, G: AUTHOR [+3]

Abstract

A fault analysis mechanism is provided for use in performing diagnostic operations on a microprogrammed large-scale data processing machine of the type employing scan ring latches. This mechanism enables the internal machine state to be quickly captured for any desired clock pulse interval of any desired microword.

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Data Processor Fault Analysis Assist

A fault analysis mechanism is provided for use in performing diagnostic operations on a microprogrammed large-scale data processing machine of the type employing scan ring latches. This mechanism enables the internal machine state to be quickly captured for any desired clock pulse interval of any desired microword.

For diagnostic purposes, various existing microprogrammed data processing machines have the ability to stop at the end of a preselected microword. This is accomplished by means of an address matching mechanism to which is supplied the control store address of the microword at the end of which it is desired to stop the machine. Unfortunately, each microword encompasses several clock pulse intervals. Thus, it may be difficult to determine the source of an error occurring early in a microword cycle because the internal state of the machine at the end of the microword may no longer be representative of its internal state at the time of the clock pulse during which the error occurred.

The subject of this technique is an extension to address match mechanisms to enable the machine to stop on any desired clock pulse during the course of any desired microword. In particular, a set of scan latches is provided on one of the clock pulse generator chips, which latches can be set by the usual scan-in mechanism to indicate the particular clock pulse on which a stop is desired. This set of latches is connected to additional logic c...