Browse Prior Art Database

Semiconductor Module

IP.com Disclosure Number: IPCOM000089500D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Benenati, JA: AUTHOR

Abstract

This semiconductor package structure is adapted to support high speed semiconductor chips with circuit densities greater than 500 circuits per chip.

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Semiconductor Module

This semiconductor package structure is adapted to support high speed semiconductor chips with circuit densities greater than 500 circuits per chip.

The substrate 10 is made of a material having a coefficient of expansion that substantially matches the coefficient of expansion of silicon. A typical material is mullite. One or more semiconductor chips (not shown) are mounted on the top surface using flip-chip bonding techniques. Preferably, chromium is used as a solder stop. The substrate 10 is provided with pins 12 and 13, positioned on a 50-mil grid, which are brazed to the bottom surface of the substrate.

Electrical connection to the top surface of the module is made between pin 12 by via 14 which is connected to metallurgy fan-out line 16 which, in turn, is connected to a device (not shown) by a solder pad 18. A metallurgy layer pattern 16, 18, 21, 22 is either provided on the top surface of the substrate 10, as in a glass metal module, or substrate 10 is a multilayer ceramic module containing vias and metallurgy lines. The pins 12 are soldered directly to a supporting board. However, engineering changes could be made by unsoldering the module, deleting the connection to the pin on the surface of the board, and wire bonding a new connection.

Coupled noise between lines on the top surface fan-out pattern from the chip to the I/O vias is reduced by having a ground plane 20 below the signal lines. The 50-mil grid of pins helps reduce the nois...