Browse Prior Art Database

I O Pad Modification

IP.com Disclosure Number: IPCOM000089501D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Uhl, C: AUTHOR

Abstract

In a semiconductor structure having first and second wiring levels, an array of I/O pads, in accordance with the configuration of Fig. 2, increases the number of usable wiring channels.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

I O Pad Modification

In a semiconductor structure having first and second wiring levels, an array of I/O pads, in accordance with the configuration of Fig. 2, increases the number of usable wiring channels.

Fig. 1 depicts a conventional I/O pad, with the small circles representing vias having wiring channels connected thereto.

Fig. 1A is a cross-sectional view taken along the line 1A-1A of Fig. 1.

Fig. 2 depicts a modified I/O pad which has a noncircular configuration. The small circles represent vias having wiring channels connected thereto.

Fig. 2A is a cross-sectional view taken along the line 2A-2A of Fig. 2.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]