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High Density Multicollector Transistor Logic

IP.com Disclosure Number: IPCOM000089518D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Najmann, K: AUTHOR [+2]

Abstract

Circuit structures which, compared to conventional injection logic, have a complementary layout and which are changed with respect to the lateral or vertical transistor zone sequence allow a high density logic concept. Figs. 1, 2A and 2B are, respectively, a circuit diagram of the proposed logic gate and the plan and sectional views of its preferred integrated structure layout.

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High Density Multicollector Transistor Logic

Circuit structures which, compared to conventional injection logic, have a complementary layout and which are changed with respect to the lateral or vertical transistor zone sequence allow a high density logic concept. Figs. 1, 2A and 2B are, respectively, a circuit diagram of the proposed logic gate and the plan and sectional views of its preferred integrated structure layout.

Each gate uses a lateral multicollector PNP transistor T1 as the active element. In place of a load resistor a current sink, in the form of transistor T2 with an N2/P4/N1 zone sequence, is used which is advantageously merged and integrated with T1 in the same isolated epi (epitaxy) region, as shown in Figs. 2A and 2B. Isolation is effected, for example, by means of a composite dielectric/junction isolation shown as a recessed oxide (ROI) / P+ frame surrounding the respective epi region.

T2 serves to control the required switching speed. Decoupling and logical combination are effected by the multicollector output, the outputs being dotted with the outputs of other gates. In practice, a fan-out of 2 - 3 occurs in most cases. For this reason a layout with 3 collectors was chosen, which can be favorably arranged in ring form around injector P4. Via the N+ diffusion (reach through) necessary for contacting, the input is connected to the N1 epitaxy. This layout leads to a very small active semiconductor surface requiring only a minimum number of conta...