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Dynamic Storage Cell with Phase Dependent Data Association

IP.com Disclosure Number: IPCOM000089521D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Huber, W: AUTHOR [+3]

Abstract

This dynamic storage cell (Fig. 1) with phase-dependent data association, which can be read and written within a storage array, permits storing data to a base > 2. In comparison with binary storage cells, the main advantage of phase-dependent data association is the essentially increased, and practically unlimited, information content of the cell. This means that at 8 phases a phase-divided oscillating storage cell has three times the capacity of a conventional storage cell.

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Dynamic Storage Cell with Phase Dependent Data Association

This dynamic storage cell (Fig. 1) with phase-dependent data association, which can be read and written within a storage array, permits storing data to a base > 2. In comparison with binary storage cells, the main advantage of phase- dependent data association is the essentially increased, and practically unlimited, information content of the cell. This means that at 8 phases a phase-divided oscillating storage cell has three times the capacity of a conventional storage cell.

A circuit arrangement with bipolar transistors for a dynamic storage cell with phase-dependent data association, capable of being operated in a storage array, will be described below by the illustrated circuit arrangement and the time diagram (Fig. 2).

Standby Mode.

Current source T1 loads base-emitter capacitor C1 of T2 until T3 is conductive (one VBE above VR1). Then current is fed to base-emitter capacitor C2 of T4.

The next negative pulse TC1 drives T5 into saturation, thus unloading C1. TC2 then unloads C2, and the whole operation is repeated.

By suitably designing C1 and current source T1,TR, a timing pulse TC1 (TC2) is frequency-divided by 3, 4, 5 or more.

Write Operation.

RWS is switched to the up level (0.7 V), enabling the base of T2. A negative pulse on TRW unloads C1 via inversely biased transistor T2, providing a defined start condition for the frequency divider cell.

Read Operation.

The collector of T2 is connected to g...