Browse Prior Art Database

MOS Gate Turn Off Lateral SCR

IP.com Disclosure Number: IPCOM000089527D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Perner, FA: AUTHOR [+2]

Abstract

Described is a surface effect SCR (semiconductor controlled rectifier) with a high speed gate turn-off feature. Fig. 1 is a cross section of the MOS (metal oxide semiconductor) gate turn-off lateral SCR. Fig. 2 shows an electrical equivalent circuit.

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MOS Gate Turn Off Lateral SCR

Described is a surface effect SCR (semiconductor controlled rectifier) with a high speed gate turn-off feature. Fig. 1 is a cross section of the MOS (metal oxide semiconductor) gate turn-off lateral SCR. Fig. 2 shows an electrical equivalent circuit.

This planer structure uses a positive feedback mechanism similar to that of an SCR to maintain current flow in a silicon switch device after being initiated with a gating pulse (latching action). Current flow in this device is at the surface of the silicon, which differentiates it from the conventional SCR in which current flow is in the bulk silicon. The surface current is controlled by a thin-oxide MOS gate over an ion-implanted channel region that effectively switches the "base region" of the SCR from a narrow base device that will support the positive feedback latch current to a wide base device that prevents current flow. This structure is controlled by the MOS gate, and is designed to have the speed characteristics of the MOS transistor. A diffused gate region is located near the cathode electrode to initiate current flow (injection) in this device.

Fabrication of the device in Fig. 1 is a basic bipolar process with the following changes:

a) The lateral spacing of the N-diffused areas (W(2)) is greater than the diffusion length of electrons in the P epi region.

(Image Omitted)

b) A phosphorus channel region is implanted between the N-diffused regions to give a depletion-mode threshold voltage on the order of -5 to -10 volts. The implanted channel stops about 5 to 10 Micron (W(1)) from the cathode N region to form a high gain lateral NPN transistor when the gate voltage is g...