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Exclusive OR Output Latch for PLA

IP.com Disclosure Number: IPCOM000089548D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Balasubramanian, PS: AUTHOR [+2]

Abstract

This technique allows the XOR logic function to be performed on the and K outputs of conventional PLA (programmable logic array) OR arrays. This XOR function is produced by modifying or personalizing the standard JK MS flip-flop, i.e., the normal circuit which is connected to the OR array output.

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Exclusive OR Output Latch for PLA

This technique allows the XOR logic function to be performed on the and K outputs of conventional PLA (programmable logic array) OR arrays. This XOR function is produced by modifying or personalizing the standard JK MS flip-flop,
i.e., the normal circuit which is connected to the OR array output.

Fig. 1 shows a standard JK MS flip-flop. The J Bar and K Bar inputs are fed into the circuit from adjacent sides and the Q and Q Bar outputs leave from the vertical lines at the center of the circuit.

Fig. 2 shows how this circuit could be personalized to produce an XOR latch. The personalization would be accomplished via metal lines and by the addition of three thin oxide transistors. The NOR of the and K inputs is produced at node A. The output from node A is fed to the opposite side of the latch and is ORed with the AND of the J and K inputs to produce the XOR functions at node C. The output from node C is fed back to the opposite side of the latch through an inverter made up of devices 1 and 2.

The truth table of Fig.3 shows the function performed on the J and K inputs.

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