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Random Test Patterns to Logic Surrounding Embedded Arrays

IP.com Disclosure Number: IPCOM000089562D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Goel, P: AUTHOR [+3]

Abstract

Straightforward random test patterns are economically very attractive for combinational logic networks but expensive for logic with embedded arrays. This arrangement restores the attractiveness of random test patterns for logic containing embedded arrays.

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Random Test Patterns to Logic Surrounding Embedded Arrays

Straightforward random test patterns are economically very attractive for combinational logic networks but expensive for logic with embedded arrays. This arrangement restores the attractiveness of random test patterns for logic containing embedded arrays.

Random test pattern generation consists of fault simulating a set of random test patterns where each test pattern is obtained by randomly assigning either a logic 1 or a logic 0 to each of the primary inputs (PIs) of the combinational logic network. The technique is extendible to level sensitive scan design logic networks by treating shift register latches (SRLs) as external inputs and external outputs, though it is necessary to treat the system and shift clocks differently from the remaining primary inputs.

Random test patterns can be extended to the case of read-only storage/random-access memory arrays embedded in combinatorial logic. The random test patterns are intended to test single stuck faults in the logic surrounding the arrays. In general, a sequence of test patterns, rather than a single pattern, is needed to propagate information through random-access memory arrays. Information is not propagated through a random-access memory array unless the control inputs to the array are sequenced properly in order to first write data into a word and then read the same word. To read (or write) an array it is often necessary to use a specific pattern on the PIs because of the possibility of having complex combinational logic between the PIs and the array control inputs.

In the figure, the logic that feeds the control inputs of a random-access memory array is depicted. In order to read the array, the PI pattern A = 0, B = 0, C = 1, D = 1, E = 0 must be read. No other pattern can cause a read operation to occur. An equiprobable assignment of 0 or 1 to the input pins A,B,C,D,E will cause a read operation with a probability of 1/32. Added to this, the address readout must have been written into earlier. For an array with 16 words (address locations) the probability of addressing the same word in two consecutive patterns is 1/16. Consequently the probability that a 2-pattern sequence will propagate information through the example array is 1/2 x 1/32 x 1/16 = 1/1024 probability of writing on first pattern.

Hence, very long test sequences will be needed if straightforward random test patterns are to be of use for logic containing embedded arrays. However, parallel fault simulation of long test sequences is expensive, since complete state information must be saved whenever the simulator selects a new group of faults to simulate. Hence, straightforward random test patterns are of little value in testing logic surrounding embedded arrays.

The following procedure permits meaningful exploitation of random test patterns in the case of read-only storage/random-access memory arrays embedded in combinational logic. Those PIs which feed the c...