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Browse Prior Art Database

Programmable Hardware Monitor

IP.com Disclosure Number: IPCOM000089568D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Vesper, AR: AUTHOR

Abstract

Hardware monitors are known in which many probes are attached to a system under test, and the probes are connected to custom-designed random logic to produce desired functions of the probe inputs. These functions may be simple or very complex. By using an uncommitted random-access memory, probe inputs may be routed to the memory as address inputs, and any desired logic function may be made to appear as an output of the memory if that logic function had previously been written into the memory. Such logic functions or data outputs from the memory may be routed directly to counters or back to address inputs in the same memory to provide a latch function without requiring latches to be physically provided.

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Programmable Hardware Monitor

Hardware monitors are known in which many probes are attached to a system under test, and the probes are connected to custom-designed random logic to produce desired functions of the probe inputs. These functions may be simple or very complex. By using an uncommitted random-access memory, probe inputs may be routed to the memory as address inputs, and any desired logic function may be made to appear as an output of the memory if that logic function had previously been written into the memory. Such logic functions or data outputs from the memory may be routed directly to counters or back to address inputs in the same memory to provide a latch function without requiring latches to be physically provided. The personalization or bit pattern for the memory may be manually generated, as from a system user interface, or the programs running in the engine of the hardware monitor could generate the personalization automatically.

Shown in the drawing is a simplified schematic diagram of a programmable hardware monitor for accomplishing the above functions. The monitor includes a bipolar read/write random-access memory 1. The reading or writing operation of memory 1 is controlled by a signal on control line 2, which at one level represents a read operation and at a second level represents a write operation. Memory 1 is addressed signals which appear on AB (address bus) 3, causing the addressed location to be accessed. Data appearing in the form of signals on DBI (data bus IN) 4 are written into the addressed location when the memory is personalized, or data from the memory is placed on DBO (data bus OUT) 5 during a read operation.

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