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All Net Probe Card Testing

IP.com Disclosure Number: IPCOM000089574D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Burdett, RC: AUTHOR [+4]

Abstract

In the testing of circuit cards for engineering and component faults, it has been customary to connect a test device to the card input and output tabs and to then run a very extensive sequence of inputs to the connections to see if the correct outputs occur. As the number of modules on a card increase and as the modules become more complex, the required test sequences become very long and involved. Such sequences require expensive test processors and a substantial time for testing a card.

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All Net Probe Card Testing

In the testing of circuit cards for engineering and component faults, it has been customary to connect a test device to the card input and output tabs and to then run a very extensive sequence of inputs to the connections to see if the correct outputs occur. As the number of modules on a card increase and as the modules become more complex, the required test sequences become very long and involved. Such sequences require expensive test processors and a substantial time for testing a card.

A new methodology described herein can reduce the long and expensive test procedures by applying design rules to make all nets on a card directly available for individual testing and by the use of short test sequences for each card net. As shown in the drawing, each card will, in addition to the usual input/output tabs 2, have a plurality of internal test points (ITP) 4 designated on the surface of the card. The circuit modules 5 are mounted to the card 1 between the ITPs, and are connected in the normal manner to card tabs 2. The methodology now requires that all other logic interconnections between modules be connected via one of the ITPs 4.

The card to be tested will be placed in a test device which will connect to each of the ITPs 4 and to all card tabs 2. The tester will drive the card 1 primary inputs 2 using single input change patterns, and will monitor all ITPs 4 and card tab 2 outputs to determine the net responses and compare them with the e...