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Anti Glitch Circuit

IP.com Disclosure Number: IPCOM000089580D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Hoffman, CR: AUTHOR

Abstract

In some terminals, such as printers and display devices, it is possible that the latch controlling voltages can receive random pulses during the time the power supply voltages are rising to their working levels. This can cause random character printing or display during the time the power voltage is coming up. To prevent such voltage glitches during power-on time, the above circuit can be utilized to provide a control level which is stable at the start of operations.

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Anti Glitch Circuit

In some terminals, such as printers and display devices, it is possible that the latch controlling voltages can receive random pulses during the time the power supply voltages are rising to their working levels. This can cause random character printing or display during the time the power voltage is coming up. To prevent such voltage glitches during power-on time, the above circuit can be utilized to provide a control level which is stable at the start of operations.

In the circuit, the voltage V(DD) at start-up is assumed to change as indicated in chart B. A pair of depletion-type FETs (field-effect transistors) 10 and 11 have their drains connected to the V(DD) line, and each has its gate connected to its source. With these connections, their source voltages at nodes 1 and 2, respectively, will tend to follow the rise of V(DD) without a lag due to their being normally conductive. Node 1 voltage will continue to follow the V(DD) (see chart
C), but an FET 12 of the enhanced-type, having its drain connected to node 2, its source grounded and its gate connected to node 1, will become conductive to the node 1 voltage exceeds its threshold voltage (TH) and will bold the node 2 voltage, as indicated in chart D. It will be seen that there will be a short time where the node 2 voltage exceeds the threshold voltage of an enhanced FET. This prevents use of the node 2 voltage as a safe control voltage, since undesired conduction could occur in some circuits of the de...