Browse Prior Art Database

Programmable Storage Address Compare

IP.com Disclosure Number: IPCOM000089586D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 9 page(s) / 224K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+2]

Abstract

An Address Compare Sync/Stop signal is generated only when main storage is accessed under certain specified conditions. All other accesses to that addressed storage location during the computer system operation are disregarded. A register in the computer system is loaded under program control with bits specifying main storage address compare conditions. This same register also is loaded with bits which indicate the size of main storage. In many computer systems the size of main storage can be increased or decreased according to the system user's requirements; however, once configured, the storage size is fixed. The register arrangement for indicating storage size eliminates the past more costly use of conventional switches and jumper wires.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 33% of the total text.

Page 1 of 9

Programmable Storage Address Compare

An Address Compare Sync/Stop signal is generated only when main storage is accessed under certain specified conditions. All other accesses to that addressed storage location during the computer system operation are disregarded. A register in the computer system is loaded under program control with bits specifying main storage address compare conditions. This same register also is loaded with bits which indicate the size of main storage. In many computer systems the size of main storage can be increased or decreased according to the system user's requirements; however, once configured, the storage size is fixed. The register arrangement for indicating storage size eliminates the past more costly use of conventional switches and jumper wires.

The computer system (Fig. 1), having the configuration control register (CCR) 20 for containing the address compare conditions (Fig. 2) and main storage size configuration (Fig. 3), also includes an address compare register (ACR) 30 which is loadable under program control with bits for specifying address compare functions, as set forth in Fig. 4.

The computer system (Fig. 1) includes a system language or main storage processor (MSP) and a control processor (CP). Both the MSP and CP can access main storage 10 using an address loaded into main storage address register (MSAR) 11 via CP system bus out (CP SBO) 12a and 12b or MSP local storage register (LSR) bus 13a and 13b. If address translation is specified by control bits in control mode register (CMR) 35 for CP operations or program mode register (PMR) 40 for MSP operations, the contents of MSAR 11 are concatenated with the contents of an address translation register (ATR) 45 selected by the five high order bits in MSAR 11 in main storage address decode logic 14 to form a real main storage address.

After MSAR 11 has been loaded and an ATR 45 has been selected, the real or logical storage address is compared with the contents of ACR 30 by exclusive OR circuitry in main storage address compare logic 15 under control of CCR bits 0-3. At this time the real storage address is also combined with CCR bits 4-7 by logic in decode logic 14 to check for invalid storage addresses. During the storage access the ATR group selection and data being read from or written into the storage location is checked under control of the high four order bits of ACR
30. Data read from or written into storage is compared with data contained in data compare registers 50a and 50b.

The CCR 20, ACR30 and data compare registers 50a and 50b are loaded from CP SBO 12a and 12b by means of an Alter/Display routine in the CP. The MSP is stopped while this loading takes place.

The detailed logic for performing the address compare function is set forth in Fig. 5. The contents of MSAR low 11a are compared by exclusive OR circuit 15a with the contents of ACR low 30a. If the two bytes compare equally, exclusive OR circuit 15a provides a signal to AND c...