Browse Prior Art Database

Multiphase Clocking System with Delay Tracking for Control and or Data Systems

IP.com Disclosure Number: IPCOM000089600D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Allen, FK: AUTHOR

Abstract

This article describes a multiphase clocking system which provides parallel delay compensation and automatic delay tracking for a control and/or data system.

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Multiphase Clocking System with Delay Tracking for Control and or Data Systems

This article describes a multiphase clocking system which provides parallel delay compensation and automatic delay tracking for a control and/or data system.

Fig. 1 shows a timing chart which indicates that signal A drives the system. Signal B, an inverted and slightly delayed signal A, is used as an auxiliary input. The idealized waveforms show signals C and F which will be used as nonoverlapping clock pulses for set and reset of the phase latches used to steer data and control. The idealized waveforms also show signals D and E which are utilized as overlapping data sample pulses so that hazard-free data is obtained. It will be noted that signal C can be used to steer data that will be sampled by D, while signal F will steer data that will be sampled by E. Signals C and F do not overlap, and signals E and F do not overlap. Outputs C, D, E and F are the more realistic forms of the idealized waveforms. It will be noted that rising outputs of the DOT ANDS are slow, and the falling outputs are fast. The terms "fast" and "slow", as used here, refer to the question of which chip will prevail if two or more chips with unequal delays are connected in parallel, as shown in Fig. 2.

The logical arrangement of latches (Fig. 2) for either Chip 1 or Chip 2 is basically an interlocking circuit to assure that the basic sequence relationship, shown for C, D, E and F, will result when signals A and B a...