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Applications of Ion Implantation to the Josephson Tunneling Technology

IP.com Disclosure Number: IPCOM000089607D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 5 page(s) / 64K

Publishing Venue

IBM

Related People

Harris, EP: AUTHOR [+3]

Abstract

Reduction of Resonance Amplitudes in Nonlinear Gates The gain of Josephson gates is a function of L/Lambda(j), where L is the junction length and Lambda(j) is the Josephson penetration depth, which is related to the maximum Josephson current density j(1) by j(1)Lambda(j) = constant. In order to maintain a fixed gain as gate dimensions are miniaturized (L decreasing), it is necessary to decrease Lambda(j) by increasing j(1). However, it is known that increasing j(1) increases electromagnetic resonance amplitudes in the gates [1]. These resonances occur at voltages V(n) = n hcPi over 2eL where L is the junction length and c is the velocity at which electromagnetic waves propagate in the junction open-ended cavity.

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Applications of Ion Implantation to the Josephson Tunneling Technology

Reduction of Resonance Amplitudes in Nonlinear Gates The gain of Josephson gates is a function of L/Lambda(j), where L is the junction length and Lambda(j) is the Josephson penetration depth, which is related to the maximum Josephson current density j(1) by j(1)Lambda(j) = constant. In order to maintain a fixed gain as gate dimensions are miniaturized (L decreasing), it is necessary to decrease Lambda(j) by increasing j(1). However, it is known that increasing j(1) increases electromagnetic resonance amplitudes in the gates [1]. These resonances occur at voltages V(n) = n hcPi over 2eL where L is the junction length and c is the velocity at which electromagnetic waves propagate in the junction open-ended cavity. Large amplitude junction resonances are undesirable in logic and memory circuits because they decrease the operating margins. Thus, it is desirable to minimize resonance amplitudes in micro- miniaturized Josephson gates.

Solutions to this problem have been put forth by Matisoo and Zappe [2], and Jutzi [3]. The solution of Matisoo and Zappe was to utilize shaping of the gate electrodes in order to alter the resonance mode spectrum and the geometric Q(n)'s associated with these modes. (Q(n) is defined as the quality factor of the n/th/ mode, corresponding to the voltage V(n) given by equation (1).) This technique has been demonstrated by Zappe to be effective for relatively large dimension junctions, but the effectiveness is diminished at very small dimensions because of edge rounding (~1 - 2 Micron radius of curvature) produced by the finite resolution of the photolithographic masking process. Jutzi's scheme is similar, in that shaping of the top junction electrode is utilized to excite several modes simultaneously, thus reducing the average energy in the lower order modes. However, he also provided a means for reducing higher-order resonance amplitudes using a grid-like structure of holes in the bottom electrode. Though this latter technique is effective, it is unattractive from the point of view of fabrication. The solution proposed in the present article attempts a similar modification of the cavity mode Q(n)'s as in the aforementioned publications, but utilizes a different technique that is applicable to the smallest technologies and is attractive from a fabrication point of view.

It has been demonstrated that ion implantation effects in superconductors, such as T(c) control, can be localized via photolithography to dimensions on the order of 1 Micron [4]. Besides altering T(c), ion implantation most likely decreases the electronic mean free path, l. In such case, the temperature dependent superconducting penetration depth Lambda(T) can be increased, since, for example, in a "dirty" alloy

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where Xi(o) is the zero temperature coherence length, and Lambda(L) is the zero temperature London penetration depth. Utilizing this technique, the ...