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Master Slave Flip Flop Using Latching Josephson Technology

IP.com Disclosure Number: IPCOM000089622D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Davidson, A: AUTHOR [+2]

Abstract

The circuit of this article allows economic construction of latches compatible with both serial and parallel information flow in a Josephson computer. A latch with this capability is crucial to testing of large-scale integration chips.

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Master Slave Flip Flop Using Latching Josephson Technology

The circuit of this article allows economic construction of latches compatible with both serial and parallel information flow in a Josephson computer. A latch with this capability is crucial to testing of large-scale integration chips.

A schematic diagram and corresponding logic diagram are shown in Figs. 1 and 2. The following reference characters and legends identify the same circuit portions in Figs. 1 and 2: A - Master Flip-Flop B - Parallel AND Gates C - Latching Slave AND Gate. The unique feature of the circuit is that functions usually performed by two AND gates and a slave flip-flop are performed instead by a single AND gate using latching logic. A register made of the new flip-flops can process information serially or in parallel. In serial operation, the flip-flop can be shifted to the end of the register. Such operation is an aid in chip testing. During ordinary operation, however, the flip-flops work in parallel, so that all bits from logic operations in one cycle are available at once for the next logic cycle. Operations in both parallel and serial modes are described below. Parallel Operation.

In this mode, the latching slave AND/gate C is not powered, and Master Flip- Flop A operates like the usual parallel-only flip-flop. Master Flip-Flop A acquires logic signals at D (Fig. 2) and latches accordingly. The bit thus stored in A is clocked to the next combinatorial network at K during a subsequent logic cycle by timing pulse t applied to parallel AND/gates B, which have been enabled by the appearance of current in one or the other of output line portions L1, L2 of Master Flip-Flop A which act as control lines...