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Browse Prior Art Database

End Cycle Clock Pulse

IP.com Disclosure Number: IPCOM000089623D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Anacker, W: AUTHOR [+2]

Abstract

This article shows two means for generating an "end cycle" clock. Both approaches are based on the latching/nonlatching behavior (Figs. 1A and 1B) of a two input latching AND gate shown schematically in Fig. 1C. Both approaches are powered by a clipped sinusoidal AC voltage. In Fig. 1C, a clipped sinusoidal voltage is applied via current limiting resistor R1 to a Josephson device J1 which, in the absence of current in control line C1, remains in the zero voltage state. A series resistor R2 connects the voltage to a second Josephson device J2 which, in the absence of current in control line C2, remains in the zero voltage state. A load RL shunts device J2.

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End Cycle Clock Pulse

This article shows two means for generating an "end cycle" clock. Both approaches are based on the latching/nonlatching behavior (Figs. 1A and 1B) of a two input latching AND gate shown schematically in Fig. 1C. Both approaches are powered by a clipped sinusoidal AC voltage. In Fig. 1C, a clipped sinusoidal voltage is applied via current limiting resistor R1 to a Josephson device J1 which, in the absence of current in control line C1, remains in the zero voltage state. A series resistor R2 connects the voltage to a second Josephson device J2 which, in the absence of current in control line C2, remains in the zero voltage state. A load RL shunts device J2.

The devices J1, J2 have threshold characteristics shown in Figs. 2A-2C. The device has its threshold controlled so that it will not switch until a value T1 is reached. The control signal 1 on J1, shown as 3 in Fig. 2B, is derived from the regulator current of the AC power supply. The control current to device J2 is adjusted to a point x on its threshold characteristic, as shown in Fig. 2C. At the beginning of the logic cycle, devices J1, J2 are biased at point a in Figs. 2A, 2C, respectively. Once the power supply current is established, point b is reached. As the current through the regulator chain of the power supply increases and is applied to J1 via its control line C1, shown as 3 in Fig. 2B, point c is reached and J1 switches to the voltage state, transferring current via resistor R2 t...