Browse Prior Art Database

Data Bus for Josephson Computers

IP.com Disclosure Number: IPCOM000089629D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 67K

Publishing Venue

IBM

Related People

Zappe, HH: AUTHOR

Abstract

Data transmissions between the main sections of a computer generally occur along a so-called data bus. In computers which incorporate Josephson devices, it is necessary that transmission along the data bus be very fast. This requires use of terminated transmission lines and with latching logic; it is difficult to use a single terminated line for the entire bus. Assuming a bus 10'' long, it will take (with a delay of 0.3 ps/mil) 3 ns to run along the entire length and an additional 3 ns to reset the current in the line. Also, by using a single transmission line, the input signals must be injected either resistively, inductively or capacitively. This is difficult if the transmission line properties and especially the intrinsically small transmission delay are to be maintained in the presence of such parallel components.

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Data Bus for Josephson Computers

Data transmissions between the main sections of a computer generally occur along a so-called data bus. In computers which incorporate Josephson devices, it is necessary that transmission along the data bus be very fast. This requires use of terminated transmission lines and with latching logic; it is difficult to use a single terminated line for the entire bus. Assuming a bus 10'' long, it will take (with a delay of 0.3 ps/mil) 3 ns to run along the entire length and an additional 3 ns to reset the current in the line. Also, by using a single transmission line, the input signals must be injected either resistively, inductively or capacitively. This is difficult if the transmission line properties and especially the intrinsically small transmission delay are to be maintained in the presence of such parallel components.

One approach which overcomes these problems is to use active repeater circuits from which signals can be distributed and to which signals can be applied bidirectionally. Obviously, signals can be retrieved any here along the bus. An important point is that a logic "1" be represented by current in the line. No timing pulses are required in the following approach.

Fig. 1 shows two repeaters 1 connected by a bus line section 2 of a data bus. As the power rail voltage V(p) is applied to power line 3, current determined by resistor R(p) flows through Josephson devices A,B,C, D,E,F. Bus line sections 2 have an impedance Z(o), and are terminated at both ends by resistors R(T) = Z(o). To apply a signal, device B is switched by current applied to control line 4 and current is transferred into line 2. This current first switches junction A via control line portion 5 of line 2, which, in turn, applies current into the left hand bus section 6. Subsequently, current in line 2 switches junction E via control line portion 7 applying current to right-hand bus section 8. Control line portion 9 of bus section 8 then switches device D. The input on...