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Read Constant Control Line to Cache

IP.com Disclosure Number: IPCOM000089637D
Original Publication Date: 1977-Nov-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Ris, FN: AUTHOR [+2]

Abstract

A technique is described for increasing the throughput of a processor by allowing commonly used program sequences to bypass synchronization bottlenecks in store-through caches. The technique involves adding a "read-constant request" control line between the processor and cache, together with logic for informing the storage sequencer that the addressed contents are constant and, hence, may be read out immediately, whereby a "read-constant request" received by the sequencer will not produce the ordinary read delay in issuing the read to memory, since the possibility of write requests is explicitly ruled out.

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Read Constant Control Line to Cache

A technique is described for increasing the throughput of a processor by allowing commonly used program sequences to bypass synchronization bottlenecks in store-through caches. The technique involves adding a "read- constant request" control line between the processor and cache, together with logic for informing the storage sequencer that the addressed contents are constant and, hence, may be read out immediately, whereby a "read-constant request" received by the sequencer will not produce the ordinary read delay in issuing the read to memory, since the possibility of write requests is explicitly ruled out.

Specifically, the system shown in the figure consists of the addition of a "read-constant request" control line 10 between the processor 12 and cache 14, together with associated sequencer logic. The control line 10 is in addition to the usual control and data lines between a processor and its storage sequencing logic, which typically include: (a) an address bus 16 used by the processor 12 to define which address is to be referenced; (b) a data bus 18 used to transfer data to the memory 20 for write operations and to the processor 12 for read operations; (c) a write request control line 22 used by the processor 12 to signal the storage sequencer 14 that the data concurrently on the data bus is to be stored at the address concurrently on the address bus; and (d) a read request control line 24 used by the processor 12 to signal the storage sequencer 14 that the location whose address is concurrently o...