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Interconnection of Logic Circuits

IP.com Disclosure Number: IPCOM000089647D
Original Publication Date: 1977-Dec-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 4 page(s) / 50K

Publishing Venue

IBM

Related People

Brown, LW: AUTHOR [+3]

Abstract

The interconnection of various types of digital logic circuits is described. Provision is made for more input/output (I/O) receivers to be driven by the same interface driver without the use of more costly interface drivers and/or receivers. These include electronic logic circuits of the transistor-transistor-logic (TTL) and diode-transistor-logic (DTL) variety. These logic circuits are interconnected in a logic net with a large number of circuits receiving the same digital signal, and a bus-like logic net where a large number of receivers are intended to be connected to the output of a single driver. The arrangements can be extended to the case where both a large number of drivers and a large number of receivers operate on the same interconnection node or bus line.

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Interconnection of Logic Circuits

The interconnection of various types of digital logic circuits is described. Provision is made for more input/output (I/O) receivers to be driven by the same interface driver without the use of more costly interface drivers and/or receivers. These include electronic logic circuits of the transistor-transistor-logic (TTL) and diode-transistor-logic (DTL) variety. These logic circuits are interconnected in a logic net with a large number of circuits receiving the same digital signal, and a bus-like logic net where a large number of receivers are intended to be connected to the output of a single driver. The arrangements can be extended to the case where both a large number of drivers and a large number of receivers operate on the same interconnection node or bus line.

It is possible to interconnect a larger number of receivers to a common logic network node than is provided for in the normal fan-out wiring rules of the logic family. The scheme is also applicable to the case of a channel or general purpose interface between a processor and a set of I/O devices where a multiplicity of logic nodes or bus lines are normally connected between the processor and I/O devices. The multiplicity of lines provides an opportunity for communicating to numerous receivers with more than one signal line.

A normal limitation of the number of receivers that can be connected to a single logic node is the DC current that each receiver must supply to the node when it is driven to the down level or active state. A normal logic driver is limited in the total amount of current that it can sink from the sum total of all the receivers and still maintain a down or active state voltage on the node within specification. Thus the combination of the input current of a receiver and the driving current capability of a driver compose the major restriction to the number of receivers that can be operated by a single driver. These limitations are overcome by providing a method for gating a receiver off when it is not the intended recipient of the logic signal on the bus, in order to provide for a larger number of receivers potentially available and connected to the bus. The control mechanism for gating the receivers is provided by an additional logical signal connected by conventional means independent of the bus with the number of receivers being increased.

Fig. 1 shows the essential ingredients of a conventional logic net where the diagram has been simplified to show only the output transistor Td of the logic circuit driving the bus, and a set of input transistors T1, T2, ...Tn, representing the input transistor of each of a set of logic receivers responsive to the digital signal on the bus Vb. In the conventional configuration the drive transistor Td must sink a current Ic equal to the sum of the current supplied by the driver load resistor RL, and the input currents of the receiver Ii1, Ii2,...Iin. One major limitation to the number...